Hardness Analysis and Instrumentation of Verilog Gate Level Code for FPGA-based Designs - Research Information System | University of Kassel

Contribution in edited book

Hardness Analysis and Instrumentation of Verilog Gate Level Code for FPGA-based Designs

Publication Details

Authors:

Khatri, A.; Hayek, A.; Börcsök, J.

Editor:

Wong, Stephan; Beck, Antonio Carlos; Bertels, Koen; Carro, Luigi

Publisher:

Springer International Publishing

Place:

Cham

Publication year:

2017

Pages range :

118-128

Book title:

Applied Reconfigurable Computing

Title of series:

Lecture Notes in Computer Science

Volume number:

10216

ISBN:

978-3-319-56257-5

DOI-Link der Erstveröffentlichung:

Authors/Editors